UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 610

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The communication reservation flowchart is illustrated below.
(Communication reservation)
Note The communication reservation operation executes a write to the IICn register when a stop
Remark
condition interrupt request occurs.
n = 0 to 2
Yes
Note
Figure 17-17. Communication Reservation Flowchart
Cancel communication
reservation
Define communication
reservation
IICn register
MSTSn bit = 0?
SET1 STTn
Wait
DI
EI
No
(Generate start condition)
←
xxH
Sets STTn bit (communication reservation).
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM).
Secures wait period set by software (see Table 17-6).
Confirmation of communication reservation
Clears user flag.
IICn register write operation
CHAPTER 17 I
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C BUS