UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 324

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(f) TMQ0 capture/compare register 0 (TQ0CCR0)
(g) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3)
If D
(INTTQ0CC0) is generated when the number of external event counts reaches (D
Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode. However,
the set value of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer
registers. When the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer
registers, compare match interrupt request signals (INTTQ0CC1 to INTTQ0CC3) are generated.
Therefore, mask the interrupt signal by using the interrupt mask flags (TQ0CCMK1 to TQ0CCMK3).
Caution When an external clock is used as the count clock, the external clock can be input only
Remark
0
is set to the TQ0CCR0 register, the counter is cleared and a compare match interrupt request signal
Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2)
from the TIQ00 pin. At this time, set the TQ0IOC1.TQ0IS1 and TQ0IOC1.TQ0IS0 bits to 00
(capture trigger input (TIQ00 pin): no edge detection).
The TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not
used in the external event count mode.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0
+ 1).
Page 308 of 870