UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 882

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Flash
memory
On-chip
debug
function
Function
FA-144GJ-UEN-A
Selection of
communication
mode
FLMD1 pin
FLMD0 pin
OCDM register
Cautions (DUC)
Cautions (other
than DUC)
Details of
Function
Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-
down resistor.
Supply a clock by creating an oscillator on the flash writing adapter (enclosed by
the broken lines).
Do not input a high level to the DRST pin.
When UARTA0 is selected, the receive clock is calculated based on the reset
command sent from the dedicated flash programmer after receiving the FLMD0
pulse.
If the V
writing and immediately after reset, isolate this signal.
Make sure that the FLMD0 pin is at 0 V when reset is released.
When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as
port pins after external reset, any of the following actions must be taken.
• Input a low level to the P05/INTP2/DRST pin.
• Set the OCDM0 bit. In this case, take the following actions.
The DRST pin has an on-chip pull-down resistor. This resistor is disconnected
when the OCDM0 flag is cleared to 0.
If a reset signal is input (from the target system or a reset signal from an internal
reset source) during RUN (program execution), the break function may
malfunction.
Even if the reset signal is masked by the mask function, the I/O buffer (port pin)
may be reset if a reset signal is input from a pin.
Pin reset during a break is masked and the CPU and peripheral I/O are not reset.
If pin reset or internal reset is generated as soon as the flash memory is rewritten
by DMM or read by the RAM monitor function while the user program is being
executed, the CPU and peripheral I/O may not be correctly reset.
In the on-chip debug mode, the DDO pin is forcibly set to the high-level output.
Do not mount a device that was used for debugging on a mass-produced product,
because the flash memory was rewritten during debugging and the number of
rewrites of the flash memory cannot be guaranteed.
Moreover, do not embed the debug monitor program into mass-produced
products.
Forced breaks cannot be executed if one of the following conditions is satisfied.
• Interrupts are disabled (DI)
• Interrupts issued for the serial interface, which is used for communication
• Standby mode is entered while standby release by a maskable interrupt is
• Mode for communication between MINICUBE2 and the target device is
The pseudo RRM function and DMM function do not operate if one of the
following conditions is satisfied.
• Interrupts are disabled (DI)
• Interrupts issued for the serial interface, which is used for communication
• Standby mode is entered while standby release by a maskable interrupt is
• Mode for communication between MINICUBE2 and the target device is
• Mode for communication between MINICUBE2 and the target device is
<1> Clear the OCDM0 bit to 0.
<2> Fix the P05/INTP2/DRST pin to low level until <1> is completed.
between MINICUBE2 and the target device, are masked
prohibited
UARTA0, and the main clock has been stopped
between MINICUBE2 and the target device, are masked
prohibited
UARTA0, and the main clock has been stopped
UARTA0, and a clock different from the one specified in the debugger is used
for communication
DD
signal is input to the FLMD1 pin from another device during on-board
Cautions
APPENDIX E LIST OF CAUTIONS
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