UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 873

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
DMA
function
(DMA
controller)
Function
DSA0 to DSA3
registers
DDA0 to DDA3
registers
DBC0 to DBC3
registers
DADC0 to
DADC3
registers
Details of
Function
When the value of the DSAn register is read, two 16-bit registers, DSAnH and
DSAnL, are read. If reading and updating conflict, the value being updated may
be read (see 18.13 Cautions).
Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers
before starting DMA transfer. If these registers are not set, the operation when
DMA transfer is started is not guaranteed.
Be sure to clear bits 14 to 10 of the DDAnH register to 0.
Set the DDAnH and DDAnL registers at the following timing when DMA transfer is
disabled (DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
When the value of the DDAn register is read, two 16-bit registers, DDAnH and
DDAnL, are read. If reading and updating conflict, a value being updated may be
read (see 18.13 Cautions).
Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers
before starting DMA transfer. If these registers are not set, the operation when
DMA transfer is started is not guaranteed.
Set the DBCn register at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers
before starting DMA transfer. If these registers are not set, the operation when
DMA transfer is started is not guaranteed.
Be sure to clear bits 15, 13 to 8, and 3 to 0 of the DADCn register to “0”.
Set the DADCn register at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of
The DS0 bit specifies the size of the transfer data, and does not control bus
sizing. If 8-bit data (DS0 bit = 0) is set, therefore, the lower data bus is not always
used.
If the transfer data size is set to 16 bits (DS0 bit = 1), transfer cannot be started
from an odd address. Transfer is always started from an address with the first bit
of the lower address aligned to 0.
If DMA transfer is executed on an on-chip peripheral I/O register (as the transfer
source or destination), be sure to specify the same transfer size as the register
size. For example, to execute DMA transfer on an 8-bit register, be sure to specify
8-bit transfer.
transfer
the next DMA transfer
transfer
the next DMA transfer
transfer
the next DMA transfer
Cautions
APPENDIX E LIST OF CAUTIONS
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