UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 437

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
13.5 Operation
13.5.1 Basic operation
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
<1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0,
<2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the sample
<3> When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and holds
<4> Set bit 9 of the successive approximation register (SAR) to set the compare voltage generation DAC to (1/2)
<5> The voltage difference between the voltage of the compare voltage generation DAC and the analog input voltage
<6> Next, bit 8 of the SAR register is automatically set and the next comparison is started. Depending on the value of
<7> This comparison is continued to bit 0 of the SAR register.
<8> When comparison of the 10 bits is complete, the valid digital result is stored in the SAR register, which is then
<9> In one-shot select mode, conversion is stopped
ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is
started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode.
& hold circuit.
the input analog voltage until A/D conversion is complete.
AV
is compared by the voltage comparator. If the analog input voltage is higher than (1/2) AV
SAR register remains set. If it is lower than (1/2) AV
bit 9, to which a result has been already set, the compare voltage generation DAC is selected as follows.
• Bit 9 = 1: (3/4) AV
• Bit 9 = 0: (1/4) AV
This compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is
manipulated as follows.
Analog input voltage ≥ Compare voltage: Bit 8 = 1
Analog input voltage ≤ Compare voltage: Bit 8 = 0
transferred to and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal
(INTAD) is generated.
once
continuous scan mode, repeat steps <2> to <8> for each channel.
Remark
Note In the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status is
REF0
Note
.
entered.
. In continuous select mode, repeat steps <2> to <8> until the ADA0M0.ADA0CE bit is cleared to 0. In
The trigger standby status means the status after the stabilization time has passed.
REF0
REF0
Note
. In one-shot scan mode, conversion is stopped after scanning
REF0
, the MSB is reset.
CHAPTER 13 A/D CONVERTER
REF0
, the MSB of the
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