UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 505

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Note These bits can only be rewritten when the CBnPWR bit = 0.
CBnTMS
CBnDIR
[In single transfer mode]
[In continuous transfer mode]
The reception complete interrupt request signal (INTCBnR) is generated.
Even if transmission is enabled (CBnTXE bit = 1), the transmission enable interrupt
If the next transmit data is written during communication (CBnSTR.CBnTSF bit =
1), it is ignored and the next communication is not started. Also, if reception-only
communication is set (CBnTXE bit = 0, CBnRXE bit = 1), the next communication
is not started even if the receive data is read during communication (CBnSTR.
CBbTSF bit = 1).
The continuous transmission is enabled by writing the next transmit data during
communication (CBnSTR.CBnTSF bit = 1). Writing the next transmission data is
enabled after a transmission enable interrupt (INTCBnT) occurrence.
If reception-only communication is set (CBnTXE bit = 0, CBnRXE bit = 1) in the
continuous transfer mode, the next reception is started continuously after a
reception complete interrupt (INTCBnR) regardless of the read operation of the
CBnRX register.
Therefore, read immediately the receive data from the CBnRX register. If this read
operation is delayed, an overrun error (CBnOVE bit = 1) occurs.
request signal (INTCBnT) is not generated.
0
1
0
1
However, CBnPWR bit = 1 can also be set at the same time as rewriting these bits.
Note
Note
MSB-first transfer
LSB-first transfer
Single transfer mode
Continuous transfer mode
Specification of transfer direction mode (MSB/LSB)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Transfer mode specification
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