UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 24

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
1.6.2
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) CPU
(2) Bus control unit (BCU)
(3) ROM
(4) RAM
(5) Interrupt controller (INTC)
(6) Clock generator (CG)
(7) Internal oscillator
(8) Timer/counter
(9) Watch timer
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits)
contribute to faster complex processing.
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU
generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an
instruction queue.
This is a 1024/768/512/384 KB flash memory mapped to addresses 0000000H to 00FFFFFH/0000000H to
00BFFFFH/0000000H to 007FFFFH/0000000H to 005FFFFH. It can be accessed from the CPU in one clock
during instruction fetch.
This is a 60/48/32 KB RAM mapped to addresses 3FF0000H to 3FFEFFFH/3FF5000H to 3FFEFFFH/3FF7000H.
It can be accessed from the CPU in one clock during data access.
This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware and
external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple
servicing control can be performed.
A main clock oscillator that generates the main clock oscillation frequency (f
generates the subclock oscillation frequency (f
the clock-through mode and is multiplied by four or eight in the PLL mode.
The CPU clock frequency (f
An internal oscillator is provided on chip. The oscillation frequency is 220 kHz (TYP.). An internal oscillator
supplies the clock for watchdog timer 2 and timer M.
Six-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and one-channel
16-bit interval timer M (TMM) are provided on chip.
This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz from the subclock or the
32.768 kHz f
Internal units
BRG
from prescaler 3). The watch timer can also be used as an interval timer for the main clock.
CPU
) can be selected from seven types: f
XT
) are available. As the main clock frequency (f
XX
, f
XX
/2, f
XX
/4, f
CHAPTER 1 INTRODUCTION
X
) and a subclock oscillator that
XX
/8, f
XX
/16, f
XX
XX
), f
/32, and f
X
is used as is in
Page 8 of 870
XT
.