UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 854

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Port
functions
Function
Cautions on
switching from
port mode to
alternate-
function mode
Cautions on
alternate-
function mode
(input)
PFn.PFnm bit
in port mode
Cautions on bit
manipulation
instruction for
port n register
(Pn)
Cautions on on-
chip debug pins
Cautions on
P05/INTP2/
DRST pin
Cautions on
P53 pin when
power is turned
on
Hysteresis
characteristics
Details of
Function
To switch from the port mode to alternate-function mode in the following order.
<1> Set the PFn register
<2> Set the PFCn and PFCEn registers: Alternate-function selection
<3> Set the corresponding bit of the PMCn register to 1: Switch to alternate-
If the PMCn register is set first, note with caution that, at that moment or
depending on the change of the pin states in accordance with the setting of the
PFn, PFCn, and PFCEn registers, unexpected operations may occur.
Regardless of the port mode/alternate-function mode, the Pn register is read and
written as follows.
• Pn register read: Read the port output latch value (when PMn.PMnm bit = 0), or
• Pn register write: Write to the port output latch
The input signal to the alternate-function block is low level when the
PMCn.PMCnm bit is 0 due to the AND output of the PMCn register set value and
the pin level. Thus, depending on the port setting and alternatefunction operation
enable timing, unexpected operations may occur. Therefore, switch between the
port mode and alternate-function mode in the following sequence.
• To switch from port mode to alternate-function mode (input)
• To switch from alternate-function mode (input) to port mode
In port mode, the PFn.PFnm bit is valid only in the output mode (PMn.PMnm bit =
0). In the input mode (PMnm bit = 1), the value of the PFnm bit is not reflected in
the buffer.
When a 1-bit manipulation instruction is executed on a port that provides both
input and output functions, the value of the output latch of an input port that is not
subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port
from input mode to output mode.
The following action must be taken if on-chip debugging is not used.
• Clear the OCDM0 bit of the OCDM register (special register) (0)
At this time, fix the P05/INTP2/DRST pin to low level from when reset by the
RESET pin is released until the above action is taken.
If a high level is input to the DRST pin before the above action is taken, it may
cause a malfunction (CPU deadlock).
Handle the P05 pin with the utmost care.
After reset by the WDT2RES signal, clock monitor (CLM), or low-voltage detector
(LVI), the P05/INTP2/DRST pin is not initialized to function as an on-chip debug
pin (DRST). The OCDM register holds the current value.
The P05/INTP2/DRST pin has an internal pull-down resistor (30 kΩ TYP.). After a
reset by the RESET pin, a pull-down resistor is connected. The pull-down resistor
is disconnected when the OCDM0 bit is cleared (0).
When the power is turned on, the following pin may output an undefined level
temporarily, even during reset.
• P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin
In port mode, the following port pins do not have hysteresis characteristics.
Set the pins to the alternate-function mode using the PMCn register and then
enable the alternatefunction operation.
Stop the alternate-function operation and then switch the pins to the port mode.
P02 to P06
P31 to P35, P38, P39
P40 to P42
P50 to P55
P90 to P97, P99, P910, P912 to P915
read the pin states (PMn.PMnm bit = 1).
Note
:
Cautions
N-ch open-drain setting
APPENDIX E LIST OF CAUTIONS
function mode
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