UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 355

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
waveform from the TOQ0k pin.
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTQ0CCk is generated when the count value of the 16-bit counter matches the value of
the CCRk buffer register.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TQ0CTL0
TQ0CTL1
When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs PWM
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The PWM waveform can be changed by rewriting the TQ0CCRm register while the counter is operating. The newly
The compare match interrupt request signal INTTQ0CC0 is generated when the 16-bit counter counts next time after its
Remark
Active level width = (Set value of TQ0CCRk register ) × Count clock cycle
Cycle = (Set value of TQ0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TQ0CCRk register)/(Set value of TQ0CCR0 register + 1)
(a) TMQ0 control register 0 (TQ0CTL0)
(b) TMQ0 control register 1 (TQ0CTL1)
Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1.
k = 1 to 3, m = 0 to 3
TQ0CE
0/1
0
TQ0EST
Figure 8-26. Register Setting for Operation in PWM Output Mode (1/3)
0
0
TQ0EEE
0/1
0
0
0
CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0
0
TQ0CKS2 TQ0CKS1 TQ0CKS0
TQ0MD2 TQ0MD1 TQ0MD0
0/1
1
0/1
0
0/1
0
Select count clock
0: Stop counting
1: Enable counting
1, 0, 0:
PWM output mode
0: Operate on count clock
1: Count external event
selected by TQ0CKS0 to
TQ0CKS2 bits
input signal
Note
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