UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 562

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
After reset: 00H
(n = 0 to 2)
(2) IIC status registers 0 to 2 (IICS0 to IICS2)
IICSn
The IICSn register indicates the status of the I
This register is read-only, in 8-bit or 1-bit units. However, the IICSn register can only be read when the IICCn.STTn
bit is 1 or during the wait period.
Reset sets this register to 00H.
Caution Accessing the IICSn register is prohibited in the following statuses. For details, see 3.4.8 (2)
Note The ALDn bit is also cleared when a bit manipulation instruction is executed for another bit in the
Condition for clearing (MSTSn bit = 0)
• When a stop condition is detected
• When the ALDn bit = 1 (arbitration loss)
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
Condition for clearing (EXCn bit = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
Condition for clearing (ALDn bit = 0)
• Automatically cleared after the IICSn register is
• When the IICEn bit changes from 1 to 0 (operation
• After reset
MSTSn
MSTSn
stop)
EXCn
ALDn
stop)
read
stop)
<7>
0
1
0
1
0
1
Accessing specific on-chip peripheral I/O registers.
•
•
Note
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
IICSn register.
R
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. The MSTSn bit is cleared to 0.
Extension code was not received.
Extension code was received.
ALDn
<6>
EXCn
<5>
Address: IICS0 FFFFFD86H, IICS1 FFFFFD96H, IICS2 FFFFFDA6H
COIn
<4>
2
Detection of extension code reception
C0n (n = 0 to 2).
Arbitration loss detection
TRCn
Master device status
<3>
Condition for setting (MSTSn bit = 1)
• When a start condition is generated
Condition for setting (EXCn bit = 1)
• When the higher four bits of the received address
Condition for setting (ALDn bit = 1)
• When the arbitration result is a “loss”.
data are either “0000” or “1111” (set at the rising
edge of the eighth clock).
ACKDn
<2>
STDn
<1>
SPDn
CHAPTER 17 I
<0>
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C BUS
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