UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 46

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) NMI status saving registers (FEPC and FEPSW)
(3) Interrupt source register (ECR)
31 to 16
15 to 0
Bit position
FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.
If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status
word (PSW) are saved to FEPSW.
The address of the instruction next to the one of the instruction under execution, except some instructions, is saved
to FEPC when an NMI occurs.
The current contents of the PSW are saved to FEPSW.
Because only one set of NMI status saving registers is available, the contents of these registers must be saved by
program when multiple interrupts are enabled.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are always
fixed to 0).
The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction.
FEPSW
The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt occurs.
This register holds the exception code of each interrupt source. Because this register is a read-only register, data
cannot be written to this register using the LDSR instruction.
FEPC
ECR
31
31
31
0
0
FECC
EICC
0
0
Bit name
0 0 0 0
0 0 0 0
26 25
Exception code of exception or maskable interrupt
Exception code of non-maskable interrupt (NMI)
0
FECC
0
0 0 0 0
0
0
0 0 0 0
16 15
(Saved PC contents)
0
0
0 0 0 0
Meaning
EICC
8 7
(Saved PSW
contents)
CHAPTER 3 CPU FUNCTION
0
0
0
Default value
00000000H
(x: Undefined)
(x: Undefined)
Default value
Default value
000000xxH
0xxxxxxxH
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