UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 604

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
17.9 Address Match Detection Method
been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the
master device, or when an extension code has been received (n = 0 to 2).
17.10 Error Detection
of the transmitting device, so the data of the IICn register prior to transmission can be compared with the transmitted IICn
data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match (n = 0 to 2).
17.11 Extension Code
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
In I
Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address has
In I
(1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (IICSn.EXCn bit) is
(2) If 11110xx0 is set to the SVAn register by a 10-bit address transfer and 11110xx0 is transferred from the master
(3) Since the processing after the interrupt request signal occurs differs according to the data that follows the extension
2
2
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
C bus mode, the status of the serial data bus pin (SDA0n) during data transmission is captured by the IICn register
set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth
clock (n = 0 to 2).
The local address stored in the SVAn register is not affected.
device, the results are as follows. Note that the INTIICn signal occurs at the falling edge of the eighth clock (n = 0
to 2).
• Higher four bits of data match: EXCn bit = 1
• Seven bits of data match:
code, such processing is performed by software.
For example, when operation as a slave is not desired after the extension code is received, set the IICCn.LRELn bit
to 1 and the CPU will enter the next communication wait state.
Slave Address
0000
0000
0000
0000
1111
000
000
001
010
0xx
Table 17-4. Extension Code Bit Definitions
R/W Bit
IICSn.COIn bit = 1
X
X
X
0
1
General call address
Start byte
CBUS address
Address that is reserved for different bus format
10-bit slave address specification
Description
CHAPTER 17 I
Page 588 of 870
2
C BUS