UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 863

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
A/D
converter
Function
ANI0 to ANI11
pins
ADA0M0
register
ADA0M1
register
Conversion time
selection in
normal
conversion
mode
(ADA0HS1 bit =
0)
Details of
Function
Make sure that the voltages input to the ANI0 to ANI11 pins do not exceed the
rated values.
In particular if a voltage of AV
value of that channel becomes undefined, and the conversion values of the other
channels may also be affected.
Accessing the ADA0M0 register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
A write operation to bit 0 is ignored.
Changing the ADA0M1.ADA0FR2 to ADA0M1.ADA0FR0 bits is prohibited while
A/D conversion is enabled (ADA0CE bit = 1).
When writing data to the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT
register in the following modes, stop the A/D conversion by clearing the ADA0CE
bit to 0. After the data is written to the register, enable the A/D conversion again
by setting the ADA0CE bit to 1.
• Normal conversion mode
• One-shot select mode/one-shot scan mode in high-speed conversion mode
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers are written
in the other modes during A/D conversion (ADA0EF bit = 1), the following will be
performed according to the mode.
• In software trigger mode
• In hardware trigger mode
To select the external trigger mode/timer trigger mode (ADA0TMD bit = 1), set the
highspeed conversion mode (ADA0M1.ADA0HS1 bit = 1). Do not input a trigger
during stabilization time that is inserted once after the A/D conversion operation is
enabled (ADA0CE bit = 1).
When not using the A/D converter, stop the operation by setting the ADA0CE bit
to 0 to reduce the power consumption.
Changing the ADA0M1 register is prohibited while A/D conversion is enabled
(ADA0M0.ADA0CE bit = 1).
To select the external trigger mode/timer trigger mode (ADA0M0.ADA0TMD bit =
1), set the high-speed conversion mode (ADA0HS1 bit = 1). Do not input a trigger
during stabilization time that is inserted once after the A/D conversion operation is
enabled (ADA0CE bit = 1).
Be sure to clear bits 6 to 4 to “0”.
Set as 2.6
During A/D conversion, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and
ADA0PFT registers are written or trigger is input, reconversion is carried out.
However, if the stabilization time end timing conflicts with the writing to these
registers, or if the stabilization time end timing conflicts with the trigger input, the
stabilization time of 64 clocks is reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the
stabilization time is reinserted. Therefore do not set the trigger input interval and
control register write interval to 64 clocks or below.
stopped
A/D conversion is stopped and started again from the beginning.
A/D conversion is stopped, and the trigger standby status is set.
μ
s ≤ conversion time ≤ 10.4
REF0
or higher is input to a channel, the conversion
Cautions
μ
s.
APPENDIX E LIST OF CAUTIONS
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