UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 177

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
5.6
5.6.1
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) Data wait control register 0 (DWC0)
Wait Function
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle
that is executed for each memory block space.
The number of wait states can be programmed by using the DWC0 register . Immediately after system reset, 7
data wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Reset sets this register to 7777H.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
Programmable wait function
Caution Be sure to clear bits 15, 11, 7, and 3 to “0”.
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do not
3. When the V850ES/JG3 is used in separate bus mode and operated at f
DWC0
After reset:
always accessed without a wait state. The on-chip peripheral I/O area is also not subject to
programmable wait, and only wait control from each peripheral function is performed.
access an external memory area until the initial settings of the DWC0 register are complete.
insert one or more waits.
DWn2
15
7777H
0
7
0
0
0
0
0
1
1
1
1
DW32
DW12
DWn1
14
0
0
1
1
0
0
1
1
6
R/W
Memory block 3
Memory block 1
DW31
DW11
DWn0
Address:
13
5
0
1
0
1
0
1
0
1
Multiplexed bus
None
1
2
3
4
5
6
7
DW30
DW10
FFFFF484H
12
4
memory block n space (n = 0 to 3)
Number of wait states inserted in
11
0
0
3
f
CHAPTER 5 BUS CONTROL FUNCTION
None
XX
≤ 20 MHz
DW22
DW02
10
2
Separate bus
Memory block 0
Memory block 2
DW21
DW01
Setting prohibited
1
9
f
XX
> 20 MHz
DW20
DW00
XX
0
8
> 20 MHz, be sure to
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