UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 50

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
3.3
3.3.1
programmer is connected, but it must be input from an external circuit in the self-programming mode.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The V850ES/JG3 has the following operation modes.
(1) Normal operation mode
(2) Flash memory programming mode
(3) On-chip debug mode
Specify the operation mode by using the FLMD0 and FLMD1 pins.
In the normal mode, input a low level to the FLMD0 pin when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
Operation Modes
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
In this mode, the internal flash memory can be programmed by using a flash programmer.
The V850ES/JG3 is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group)
communication specifications.
For details, see CHAPTER 28 ON-CHIP DEBUG FUNCTION.
Specifying operation mode
Remark
Operation When Reset Is Released
FLMD0
H
H
L
L: Low-level input
H: High-level input
×: Don’t care
FLMD1
H
×
L
Normal operation mode
Flash memory programming mode
Setting prohibited
Operation Mode After Reset
CHAPTER 3 CPU FUNCTION
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