UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 648

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(5) Procedure of temporarily stopping DMA transfer (clearing Enn bit)
(6) Memory boundary
(7) Transferring misaligned data
(b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly
Stop and resume the DMA transfer under execution using the following procedure.
<1> Suppress a transfer request from the DMA request source (stop the operation of the on-chip peripheral I/O).
<2> Check the DMA transfer request is not held pending, by using the DFn bit (check if the DFn bit = 0).
<3> If it has been confirmed that no DMA transfer request is held pending, clear the Enn bit to 0 (this operation
<4> Set the Enn bit to 1 to resume DMA transfer.
<5> Resume the operation of the DMA request source that has been stopped (start the operation of the on-chip
The operation is not guaranteed if the address of the transfer source or destination exceeds the area of the DMA
target (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer.
DMA transfer of misaligned data with a 16-bit bus width is not supported.
If an odd address is specified as the transfer source or destination, the least significant bit of the address is forcibly
assumed to be 0.
<1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop operation
<2> Check that the DMA transfer request of the channel to be forcibly terminated is not held pending, by using
<3> When it has been confirmed that the DMA request of the channel to be forcibly terminated is not held
<4> Again, clear the Enn bit of the channel to be forcibly terminated.
<5> Copy the initial number of transfers of the channel to be forcibly terminated to a general-purpose register.
<6> Set the INITn bit of the channel to be forcibly terminated to 1.
<7> Read the value of the DBCn register of the channel to be forcibly terminated, and compare it with the
Remarks 1. When the value of the DBCn register is read in <7>, the initial number of transfers is read if
If a request is pending, wait until execution of the pending DMA transfer request is completed.
stops DMA transfer).
peripheral I/O).
of the on-chip peripheral I/O).
the DTFRn.DFn bit. If a DMA transfer request is held pending, wait until execution of the pending request
is completed.
pending, clear the Enn bit to 0.
If the target of transfer for the channel to be forcibly terminated (transfer source/destination) is the internal
RAM, execute this operation once more.
value copied in <5>. If the two values do not match, repeat operations <6> and <7>.
2. Note that method (b) may take a long time if the application frequently uses DMA transfer for a
forced termination has been correctly completed. If not, the remaining number of transfers is
read.
channel other than the DMA channel to be forcibly terminated.
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
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