UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 283

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UPD70F3740GC-UEU-AX

Manufacturer Part Number
UPD70F3740GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3740GC-UEU-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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V850ES/JG3
7.5.7
to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in
the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
signal (INTTPnCCm) occurs.
register for the unused pins.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set
The interval of the valid edge can be measured by reading the TPnCCRm register after a capture interrupt request
Select either the TIPn0 or TIPn1 pin as the capture trigger input pin. Specify “No edge detected” by using the TPnIOC1
Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110)
input/capture
trigger input)
trigger input)
event count
Remark
TIPn0 pin
TIPn1 pin
(external
(capture
Internal count clock
n = 0 to 5
m = 0, 1
Figure 7-34. Configuration in Pulse Width Measurement Mode
detector
detector
detector
Edge
Edge
Edge
selection
TPnCE bit
Count
clock
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TPnCCR0 register
(capture)
TPnCCR1 register
Clear
16-bit counter
(capture)
INTTPnOV
INTTPnCC0
INTTPnCC1
signal
signal
signal
Page 267 of 870

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