UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 462

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
14.4.3 Cautions
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Observe the following cautions when using the D/A converter of the V850ES/JG3.
(1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output
(2) Before changing the operation mode, be sure to clear the DA0M.DA0CEn bit to 0.
(3) When using one of the P10/AN00 and P11/AN01 pins as an I/O port and the other as a D/A output pin, do so in an
(4) Make sure that AV
(5) Apply power to AV
(6) No current can be output from the ANOn pin (n = 0, 1) because the output impedance of the D/A converter is high.
(7) Because the D/A converter stops operation in the STOP mode, the ANO0 and ANO1 pins go into a high-impedance
mode.
application where the port I/O level does not change during D/A output.
When connecting a resistor of 2 MΩ or less, insert a JFET input operational amplifier between the resistor and the
ANOn pin.
state, and the power consumption can be reduced.
In the IDLE1, IDLE2, or subclock operation mode, however, the operation continues.
consumption, therefore, clear the DA0M.DA0CEn bit to 0.
REF0
REF1
= V
at the same timing as AV
DD
= AV
Figure 14-2. External Pin Connection Example
REF1
AV
AV
ANOn
AV
REF0
REF1
= 3.0 to 3.6 V. If this range is exceeded, the operation is not guaranteed.
SS
REF0
0.1 F
0.1 F
.
−
+
μ
μ
JFET input
operational amplifier
10 F
10 F
μ
μ
Output
V
DD
CHAPTER 14 D/A CONVERTER
To lower the power
Page 446 of 870