UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 630

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
18.3 Registers
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) DMA source address registers 0 to 3 (DSA0 to DSA3)
Cautions 1. Be sure to clear bits 14 to 10 of the DSAnH register to 0.
The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3).
These registers are divided into two 16-bit registers, DSAnH and DSAnL.
These registers can be read or written in 16-bit units.
2. Set the DSAnH and DSAnL registers at the following timing when DMA transfer is disabled
3. When the value of the DSAn register is read, two 16-bit registers, DSAnH and DSAnL, are
4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
(n = 0 to 3)
(n = 0 to 3)
DSAnH
DSAnL
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
read. If reading and updating conflict, the value being updated may be read (see 18.13
Cautions).
starting DMA transfer. If these registers are not set, the operation when DMA transfer is
started is not guaranteed.
After reset: Undefined
DMA transfer
SA15 SA14 SA13 SA12
SA25 to SA16
SA15 to SA0
IR
IR
0
1
0
External memory or on-chip peripheral I/O
Internal RAM
Set the address (A25 to A16) of the DMA transfer source
(default value is undefined).
During DMA transfer, the next DMA transfer source address is held.
When DMA transfer is completed, the DMA address set first is held.
Set the address (A15 to A0) of the DMA transfer source
(default value is undefined).
During DMA transfer, the next DMA transfer source address is held.
When DMA transfer is completed, the DMA address set first is held.
0
R/W
0
SA11
0
Address: DSA0H FFFFF082H, DSA1H FFFFF08AH,
SA10
0
Specification of DMA transfer source
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
SA25
SA9
DSA2H FFFFF092H, DSA3H FFFFF09AH,
DSA0L FFFFF080H, DSA1L FFFFF088H,
DSA2L FFFFF090H, DSA3L FFFFF098H
SA24
SA8
SA23
SA7
SA22 SA21 SA20 SA19 SA18 SA17 SA16
SA6 SA5 SA4 SA3 SA2 SA1 SA0
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