UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 676

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
19.5 Exception Trap
V850ES/JG3, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
19.5.1 Illegal opcode definition
sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal instruction is
executed.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a
Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is recommended
(1) Operation
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control.
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
The processing of the exception trap is shown below.
that it not be used.
x: Arbitrary
15
x
x
x
x
11
x
CPU processing
10
1
1
1
Figure 19-11. Exception Trap Processing
1
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
1
1
5
4
x
x
x
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
x
Exception trap (ILGOP) occurs
0
x
31
Exception processing
x
x
x
Restored PC
PSW
1
1
1
00000060H
x
27 26
x
0
1
1
1
to
1
1
23 22
1
1
x x x x x x 0
16
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