UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 366

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and a capture interrupt request signal
(INTTQ0CCm) is generated.
generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TQ0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by
software.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
INTTQ0CC0 signal
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
TQ0CCR0 register
TQ0CCR1 register
TQ0CCR2 register
TQ0CCR3 register
INTTQ0OV signal
TIQ00 pin input
TIQ01 pin input
TIQ02 pin input
TIQ03 pin input
16-bit counter
Figure 8-30. Basic Timing in Free-Running Timer Mode (Capture Function)
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
0000
0000
0000
0000
D
20
D
00
D
30
D
10
CLR instruction
D
Cleared to 0 by
00
CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
D
D
20
D
01
D
10
30
D
11
D
21
D
31
D
01
Cleared to 0 by
CLR instruction
D
11
D
12
D
D
21
D
02
31
D
22
D
32
D
D
Cleared to 0 by
CLR instruction
02
12
D
03
D
D
D
13
32
22
D
D
33
03
D
23
D
13
D
D
33
23
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