UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 60

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
3.4.5
when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by
an instruction for operand data. Because the number of general-purpose registers that can be used as a pointer is limited,
however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many
general-purpose registers as possible can be secured for variables, and the program size can be reduced.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The architecture of the V850ES/JG3 requires that a register that serves as a pointer be secured for address generation
(1) Program space
(2) Data space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid.
Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H
unconditionally corresponds to the memory map.
To use the internal RAM area as the program space, access addresses 03FF0000H to 03FFEFFFH.
Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation (invalid
With the V850ES/JG3, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space.
Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an
address.
Recommended use of address space
fetch) straddling the on-chip peripheral I/O area does not occur.
CHAPTER 3 CPU FUNCTION
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