UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 314

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
the count clock, and the counter starts counting. At this time, the output of the TOQ00 pin is inverted. Additionally, the set
value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
to 0000H, the output of the TOQ00 pin is inverted, and a compare match interrupt request signal (INTTQ0CC0) is
generated.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TQ0CTL0
TQ0CTL1
When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
The interval can be calculated by the following expression.
Interval = (Set value of TQ0CCR0 register + 1) × Count clock cycle
Note This bit can be set to 1 only when the interrupt request signals (INTTQ0CC0 and INTTQ0CCk) are masked
(a) TMQ0 control register 0 (TQ0CTL0)
(b) TMQ0 control register 1 (TQ0CTL1)
by the interrupt mask flags (TQ0CCMK0 to TQ0CCMKk) and the timer output (TOQ0k) is performed at the
same time. However, the TQ0CCR0 and TQ0CCRk registers must be set to the same value (see 8.5.1 (2)
(d) Operation of TQ0CCR1 to TQ0CCR3 registers) (k = 1 to 3).
TQ0CE
0/1
0
TQ0EST
0
0
Figure 8-4. Register Setting for Interval Timer Mode Operation (1/2)
TQ0EEE
0/1
0
Note
0
0
0
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0CKS2 TQ0CKS1 TQ0CKS0
TQ0MD2 TQ0MD1 TQ0MD0
0/1
0
0/1
0
0/1
0
Select count clock
0: Stop counting
1: Enable counting
0, 0, 0:
Interval timer mode
0: Operate on count
1: Count with external
clock selected by bits
TQ0CKS0 to TQ0CKS2
event count input signal
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