UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 703

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Item
Main clock oscillator
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
(2) Releasing STOP mode by reset
Notes 1. If the STOP mode is set while the A/D converter is operating, the A/D converter is automatically stopped and
The same operation as the normal reset operation is performed.
2. Even if the STOP mode is set while the A/D converter is operating, the power consumption is reduced
3. If the STOP mode is set while the D/A converter is operating, the D/A converter is automatically stopped and
4. Even if the STOP mode is set while the D/A converter is operating, the power consumption is reduced
starts operating again after the STOP mode is released. However, in that case, the A/D conversion results
after the STOP mode is released are invalid. All the A/D conversion results before the STOP mode is set are
invalid.
equivalently to when the A/D converter is stopped before the STOP mode is set.
the pin status becomes high impedance. After the STOP mode is released, D/A conversion resumes, the
setting time elapses, and the status returns to the output level before the STOP mode was set.
equivalently to when the D/A converter is stopped before the STOP mode is set.
Setting of STOP Mode
CSIB0 to CSIB4
I
UARTA0 to UARTA2
2
C00 to I
2
C02
Table 21-9. Operating Status in STOP Mode
Stops oscillation
Oscillation enabled
Stops operation
Stops operation
Stops operation
Stops operation (but standby mode release is possible)
Stops operation
Stops operation
Operable when f
count clock
Stops operation
Operable when f
count clock
Operable when the SCKBn input clock is selected as the count clock (n = 0 to 4)
Stops operation
Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
Stops operation (conversion result undefined)
Stops operation
Stops operation (output held)
Operable
Stops operation
See 2.2 Pin States.
Retains status before STOP mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the STOP mode was set.
When Subclock Is Not Used
Notes 3, 4
R
R
/8 is selected as the
is selected as the
−
(high impedance is output)
Operating Status
CHAPTER 21 STANDBY FUNCTION
Oscillation enabled
Operable when f
the count clock
Operable when f
count clock
Operable when f
the count clock
Notes 1, 2
When Subclock Is Used
R
XT
R
/8 or f
or f
is selected as the
XT
XT
is selected as
is selected as
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