UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1010

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.3.6 In-service priority register (ISPR)
request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt signal request
is set to 1 and remains set while the interrupt is serviced.
priority is automatically cleared to 0 by hardware. However, it is not cleared to 0 when execution is returned from non-
maskable interrupt servicing or exception processing.
1008
The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt
When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution In the interrupt enabled (EI) state, if an interrupt is acknowledged during the reading of the ISPR
Remark
register, the value of the ISPR register may be read after the bit is set (1) by this interrupt
acknowledgment.
acknowledgment, read it in the interrupt disabled (DI) state.
n: 0 to 7 (priority level)
After reset: 00H
ISPR
ISPRn
ISPR7
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
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0
1
Interrupt request signal with priority n is not acknowledged
Interrupt request signal with priority n is being acknowledged
R
ISPR6
To read the value of the ISPR register properly before interrupt
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Address: FFFFF1FAH
ISPR5
Priority of interrupt currently being acknowledged
User’s Manual U18279EJ3V0UD
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ISPR4
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ISPR3
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ISPR2
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ISPR1
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ISPR0
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