UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 945

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Address wait control register (AWC)
This register is used to secure the setup and hold time for the address latch.
The AWC register can set an address setup wait state or address hold wait state that is to be inserted in each
bus cycle. The address setup wait state is inserted before T1 state and the address hold wait state is
inserted after T1 state.
Address setup wait state and address hold wait state insertion can be set with the AWC register for each CS
space.
This register can be read or written in 16-bit units.
Reset sets this register to FFFFH.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to
Caution Be sure to set bits 4 to 15 to “1”. If they are set to “0”, the operation is not guaranteed.
CSn signal
CSn signal
After reset: FFFFH
2. During address setup wait state and address hold wait state, the WAIT pin-based
3. Write to the AWC register after reset, and then do not change the set values. Also,
AWC
address setup wait state and address hold wait state insertion.
external wait function is disabled.
when changing the initial values of the AWC register, do not access an external memory
area until the settings are complete.
AHWn
ASWn
15
1
7
1
0
1
0
1
Specification of address setup wait state inserted in each CSn space (n = 0, 1)
Specification of address hold wait state inserted in each CSn space (n = 0, 1)
Not inserted
Inserted
Not inserted
Inserted
CHAPTER 18 BUS CONTROL FUNCTION
R/W Address: FFFFF488H
14
1
1
6
User’s Manual U18279EJ3V0UD
13
1
1
5
12
1
4
1
AHW1
11
1
3
CS1
ASW1
10
1
2
AHW0
1
9
1
CS0
ASW0
1
8
0
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