UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1178

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1176
←
GR [ ]
SR [ ]
zero-extend (n)
sign-extend (n)
load-memory (a, b)
store-memory (a, b, c)
load-memory-bit (a, b)
store-memory-bit (a, b, c)
saturated (n)
result
Byte
Halfword
Word
+
–
ll
×
÷
%
AND
OR
XOR
NOT
logically shift left by
logically shift right by
arithmetically shift right by
i
r
l
Register Symbol
(3) Register symbols used in operations
(4) Register symbols used in execution clock
Register Symbol
If executing another instruction immediately after executing the first instruction (issue).
If repeating execution of the same instruction immediately after executing the first instruction (repeat).
If using the results of instruction execution in the instruction immediately after the execution (latency).
Input for
General-purpose register
System register
Expand n with zeros until word length.
Expand n with signs until word length.
Read size b data from address a.
Write data b into address a in size c.
Read bit b of address a.
Write c to bit b of address a.
Execute saturated processing of n (n is a 2’s complement).
If, as a result of calculations,
Reflects the results in a flag.
Byte (8 bits)
Half word (16 bits)
Word (32 bits)
Addition
Subtraction
Bit concatenation
Multiplication
Division
Remainder from division results
Logical product
Logical sum
Exclusive OR
Logical negation
Logical shift left
Logical shift right
Arithmetic shift right
n ≥ 7FFFFFFFH, let it be 7FFFFFFFH.
n ≤ 80000000H, let it be 80000000H.
APPENDIX C INSTRUCTION SET LIST
User’s Manual U18279EJ3V0UD
Explanation
Explanation