UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 870

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

868
IICF0
After reset: 00H
Note Bits 6 and 7 are read-only bits.
Cautions 1. Write to the STCEN0 bit only when the operation is stopped (IICE0 bit = 0).
Condition for clearing (STCEN0 bit = 0)
• Detection of start condition
• Reset
Condition for clearing (IICRSV0 bit = 0)
• Clearing by instruction
• Reset
IICBSY0
STCEN0
IICRSV0
Condition for clearing (STCF0 bit = 0)
• Clearing by setting the STT0 bit = 1
• When the IICE0 bit = 1 → 0 (operation stop)
• Reset
Condition for clearing (IICBSY0 bit = 0)
• Detection of stop condition
• When the IICE0 bit = 1 → 0 (operation stop)
• Reset
STCF0
STCF0
<7>
0
1
0
1
2. As the bus release status (IICBSY0 bit = 0) is recognized regardless of the actual bus
3. Write to the IICRSV0 bit only when the operation is stopped (IICE0 bit = 0).
0
1
0
1
status when the STCEN0 bit = 1, when generating the first start condition (STT0 bit =
1), it is necessary to verify that no third party communications are in progress in order
to prevent such communications from being destroyed.
Generate start condition
Start condition generation unsuccessful: clear STT0 flag
Bus release status (initial communication status when STCEN0 bit = 1)
Bus communication status (initial communication status when STCEN0 bit = 0)
IICBSY0
Enable communication reservation
Disable communication reservation
After operation is enabled (IICE0 bit = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE0 bit = 1), enable generation of a start condition without detecting
a stop condition.
R/W
<6>
Note
Address: FFFFFD8AH
5
0
User’s Manual U18279EJ3V0UD
Communication reservation function disable bit
4
0
CHAPTER 17 I
3
0
Initial start enable trigger
IICC0.STT0 clear flag
I
2
C bus status flag
2
C BUS
Condition for setting (STCF0 bit = 1)
• Generating start condition unsuccessful and the
Condition for setting (IICBSY0 bit = 1)
• Detection of start condition
• Setting of the IICE0 bit when the STCEN0 bit = 0
Condition for setting (IICRSV0 bit = 1)
• Setting by instruction
Condition for setting (STCEN0 bit = 1)
• Setting by instruction
2
0
STT0 bit cleared to 0 when communication
reservation is disabled (IICRSV0 bit = 1).
STCEN0
<1>
IICRSV0
<0>