UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 883

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6.7 Wait state cancellation method
conflict between the SDA line change timing and IIC0 register write timing may result in the data output to the SDA line
may be incorrect.
communication, enabling wait state to be cancelled.
be exited, enabling wait state to be cancelled.
In the case of I
• By writing data to the IIC0 register
• By setting the IICC0.WREL0 bit to 1 (wait state cancellation)
• By setting the IICC0.STT0 bit to 1 (start condition generation)
• By setting the IICC0.SPT0 bit to 1 (stop condition generation)
Note Master only
If any of these wait state cancellation actions is performed, I
When canceling wait state and sending data (including address), write data to the IIC0 register.
To receive data after canceling wait state, or to end data transmission, set the WREL0 bit to 1.
To generate a restart condition after canceling wait state, set the STT0 bit to 1.
To generate a stop condition after canceling wait state, set the SPT0 bit to 1.
Execute cancellation only once for each wait state.
For example, if data is written to the IIC0 register following wait state cancellation by setting the WREL0 bit to 1,
Even in other operations, if communication is stopped halfway, clearing the IICC0.IICE0 bit to 0 will stop
If the I
2
C bus dead-locks due to noise, etc., setting the IICC0.LREL0 bit to 1 causes the communication operation to
2
C, wait state can be canceled normally in the following ways.
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
2
2
C will cancel wait state and restart communication.
C BUS
Note
Note
881