UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 410

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.4
408
(1) TMTn control register 0 (TTnCTL0)
Note The TTnOPT0.TTnOVF bit and the 16-bit counter are reset simultaneously. Moreover, timer outputs
Cautions 1. Set the TTnCKS2 to TTnCKS0 bits when the TTnCE bit = 0.
Remark
Registers
The TTnCTL0 register is an 8-bit register that controls the operation of TMTn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TTnCTL0 register by software.
(TOT00 (V850E/IG3 only), TOT01 (V850E/IG3 only), TOT10, and TOT11 pins) are reset to the TTmIOC0
register set status at the same time as the 16-bit counter is reset (V850E/IF3: m = 1, V850E/IG3: m = 0,
1).
2. Be sure to set bits 3 to 6 to “0”.
f
XX
TTnCTL0
(n = 0, 1)
: Peripheral clock
When the value of the TTnCE bit is changed from 0 to 1, the TTnCKS2 to TTnCKS0 bits can
be set simultaneously.
After reset: 00H
TTnCKS2
TTnCE
TTnCE
<7>
0
1
0
0
0
0
1
1
1
1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
TMTn operation disabled (TMTn reset asynchronously
TMTn operation enabled. TMTn operation start
TTnCKS1
R/W
6
0
0
0
1
1
0
0
1
1
Address: TT0CTL0 FFFFF580H, TT1CTL0 FFFFF5C0H
User’s Manual U18279EJ3V0UD
TTnCKS0
5
0
0
1
0
1
0
1
0
1
f
f
f
f
f
f
f
f
XX
XX
XX
XX
XX
XX
XX
XX
/2
/4
/8
/16
/64
/256
/1024
/2048
4
0
TMTn operation control
Internal count clock selection
3
0
TTnCKS2 TTnCKS1 TTnCKS0
2
Note
)
1
0