UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 370

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PWM waveform from the TOBnb pin.
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and
the 16-bit counter is cleared to 0000H.
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTBnCCb is generated when the count value of the 16-bit counter matches
the value of the CCRb buffer register.
368
TABnCTL1
TABnCTL0
When the TABnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The PWM waveform can be changed by rewriting the TABnCCRa register while the counter is operating. The newly
The compare match interrupt request signal INTTBnCC0 is generated when the 16-bit counter counts next time
Remark
Active level width = (Set value of TABnCCRb register) × Count clock cycle
Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TABnCCRb register)/(Set value of TABnCCR0 register + 1)
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
n = 0, 1
a = 0 to 3
b = 1 to 3
TABnCE
0/1
0
TABnEST
Figure 7-30. Setting of Registers in PWM Output Mode (1/3)
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
TABnEEE
0/1
0
User’s Manual U18279EJ3V0UD
0
0
0
0
TABnMD2 TABnMD1TABnMD0
TABnCKS2 TABnCKS1 TABnCKS0
0/1
1
0/1
0
0/1
0
1, 0, 0:
PWM output mode
0: Operate on count clock
1: Count with external
Select count clock
0: Stop counting
1: Enable counting
selected by TABnCKS0 to
TABnCKS2 bits
event count input signal
Note