UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 982

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.10 Forcible Termination
980
(internal signal)
(internal signal)
(internal signal)
DMA transfer can be forcibly terminated by the DCHCn.INITn bit (n = 0 to 3).
An example of forcible termination by the DCHCn.INITn bit is illustrated below (n = 0 to 3).
(b) When transfer is suspended during DMA channel 1 block transfer, and transfer under another
Remark
DMARQ2
DMARQ3
DMARQ1
condition is executed
(a) Block transfer via DMA channel 3 is started during block transfer via DMA channel 2
The values of the DSAn, DDAn, and DBCn registers (n = 0 to 3) are retained even when DMA
transfer is forcibly terminated, because these registers are FIFO-format buffer registers. The next
transfer condition can be set to these registers even while DMA transfer is in progress. On the other
hand, the setting of the DADCn and DCHCn registers is invalid during DMA transfer because these
registers are not buffer registers (see 19.8
addressing control registers 0 to 3 (DADC0 to DADC3), and 19.3.5 DMA channel control
registers 0 to 3 (DCHC0 to DCHC3)).
CPU CPU CPU CPU DMA2 DMA2 DMA2 DMA2 DMA2 CPU DMA3 DMA3 DMA3 DMA3 CPU CPU CPU
CPU CPU CPU CPU DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 CPU CPU CPU CPU DMA1 DMA1 DMA1 CPU
DSA1, DDA1, DBC1,
DADC1, DCHC1
E22 bit = 1
TC2 bit = 0
DSA2, DDA2, DBC2,
DADC2, DCHC2
E11 bit = 1
TC1 bit = 0
Figure 19-9. Example of Forcible Termination of DMA Transfer
Register set
DSA3, DDA3, DBC3,
DADC3, DCHC3
Register set
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
E33 bit = 1
TC3 bit = 0
Register set
DSA1, DDA1,
DBC1
User’s Manual U18279EJ3V0UD
Register set
DCHC2
(INIT2 bit = 1)
DCHC1
(INIT1 bit = 1)
E11 bit → 0
TC1 bit = 0
Next Address Setting Function, 19.3.4
Forcible termination of DMA channel 2 transfer, bus released
E22 bit → 0
TC2 bit = 0
Register set
Forcible termination of DMA channel
1 transfer, bus released
Register set
DMA channel 3 transfer start
E11 bit → 1
TC1 bit = 0
DADC1,
DCHC1
Register set
DMA channel 3 terminal count
E33 bit → 0
TC3 bit → 1
DMA channel 1
terminal count
E11 bit → 0
TC1 bit → 1
DMA