UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 694

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

692
(1) A/D converter 2 mode register 0 (AD2M0)
Cautions 1. Writing to bit 0 is ignored.
The AD2M0 register is a register that specifies the operation mode and controls conversion operations.
This register can be read or written in 8-bit or 1-bit units. However, bit 0 is read-only.
Reset sets this register to 00H.
2. The conversion resolution of the pin to which an analog signal is input first immediately
3. A/D conversion is stopped and started again from the beginning if the AD2M0 and AD2S
4. Be sure to set bits 1 to 3 to “0”.
AD2M0
after A/D conversion is started may drop. For details, see 13.7 (6) About AV
registers are written during A/D conversion operation (AD2EF bit = 1).
After reset: 00H
AD2MD1
•
•
•
AD2CE
AD2PS
AD2EF
AD2CE
The first result of conversion by the A/D converter 2 becomes valid when the
AD2CE bit is set to 1 (when conversion is enabled) at least 2 s after the AD2PS
bit is set to 1 (A/D power is turned on).
If the AD2CE bit is set to 1 before 2 s pass, the conversion operation is started
and ends after the A/D conversion time, but the conversion result is undefined.
When the A/D converter 2 is not used, set to 0 the AD2CE bit (stop conversion
operation) and the AD2PS bit (turn off A/D power) to reduce the power
consumption.
Do not set the AD2PS2 bit during A/D conversion operation (AD2EF bit = 1).
While the A/D conversion operation is not performed, the AD2CE and AD2PS bits
can be simultaneously cleared to 0.
<7>
0
1
0
1
0
0
1
1
0
1
R/W
AD2MD0
Conversion operation stopped
Conversion operation enabled
A/D power off
A/D power on
During A/D conversion stop
During A/D conversion operation
AD2PS
6
0
1
0
1
Address: FFFFFB80H
CHAPTER 13 A/D CONVERTER 2
AD2MD1 AD2MD0
User’s Manual U18279EJ3V0UD
Successive select mode
Successive scan mode
One-shot select mode
One-shot scan mode
5
Control of A/D conversion operation
Status of A/D converter 2 (status)
Specification of operation mode
4
A/D conversion control
µ
3
0
2
0
µ
1
0
AD2EF
0
DD2
pin.