UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 865

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note Set the SPT0 bit to 1 only in master mode. However, the SPT0 bit must be set to 1 and a stop
Caution When the IICS0.TRC0 bit is set to 1, the WREL0 bit is set to 1 during the ninth clock
Remark
Cautions concerning setting timing
For master reception:
For master transmission: A stop condition may not be generated normally during the ACK period. Set to 1
• Cannot be set to 1 at the same time as the STT0 bit.
• The SPT0 bit can be set to 1 only when in master mode
• When the WTIM0 bit has been cleared to 0, if the SPT0 bit is set to 1 during the wait period that follows output
• When the SPT0 bit is set to 1, setting the SPT0 bit to 1 again is disabled until the setting is cleared to 0.
Condition for clearing (SPT0 bit = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• When the LREL0 bit = 1 (exit from communications)
• When the IICE0 bit = 0 (operation stop)
• Reset
SPT0
of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock.
The WTIM0 bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the
SPT0 bit should be set to 1 during the wait period that follows output of the ninth clock.
0
1
condition generated before the first stop condition is detected following the switch to operation
enable status. For details, see 17.15 Cautions.
and wait is canceled, after which the TRC0 bit is cleared to 0 and the SDA line is set
to high impedance.
The SPT0 bit is 0 if it is read after data setting.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDA line goes to low level, either set the SCL line to high level or wait until the SCL pin
goes to high level. Next, after the rated amount of time has elapsed, the SDA line is changed from
low level to high level and a stop condition is generated.
Cannot be set to 1 during transfer. Can be set to 1 only when the ACKE0 bit has
been cleared to 0 and during the wait period after slave has been notified of final
reception.
during the wait period that follows output of the ninth clock.
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
Stop condition trigger
Note
.
2
C BUS
Condition for setting (SPT0 bit = 1)
• Set by instruction
(4/4)
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