UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 709

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.5 Operation in Software Trigger Mode
from the beginning.
When the AD2M0.AD2CE bit is set to 1, A/D conversion is started.
When A/D conversion is started, the AD2M0.AD2EF bit = 1 (conversion in progress).
If the AD2M0 and AD2S registers are written during A/D conversion, the conversion is stopped and executed again
(1) Operation in software trigger continuous select mode
Remark
(1) The AD2CE bit = 1 (enable)
(2) The ANI22 pin is A/D-converted
(3) The conversion result is stored in the AD2CR2 register
(4) The AD2M0.AD2EF bit = 0
Remark
In this mode, one analog input pin (ANI2n) specified by the AD2S register is A/D-converted once. The
conversion results are stored in one AD2CRn register. The ANI2n pin and AD2CRn register correspond one to
one.
Each time an A/D conversion is executed, an A/D2 conversion end interrupt request signal (INTAD2) is
generated and A/D conversion ends. After A/D conversion ends, the conversion is repeated again unless the
AD2M0.AD2CE bit is set to 0.
It is not necessary to set (1) the AD2M0.AD2CE bit to restart A/D conversion
Note In the software trigger continuous select mode, the A/D conversion operation is not stopped unless the
This mode is suitable for applications in which the A/D conversion value of one analog input pin is read.
ANI2n
Analog Input Pin
Figure 13-8. Operation Example of Software Trigger Continuous Select Mode: V850E/IG3
This is an operation example with the following setting.
AD2M0.AD2MD1 and AD2M0.AD2MD0 bits = 00, AD2S.AD2S2 to AD2S.AD2S0 bits = 010
AD2M0
AD2M0.AD2CE bit is set to 0. If the AD2CRn register is not read before the next A/D conversion ends,
it is overwritten.
V850E/IF3: n = 0 to 3
V850E/IG3: n = 0 to 7
AD2CRn
A/D Conversion Result Register
ANI20
ANI21
ANI22
ANI23
ANI24
ANI25
ANI26
ANI27
CHAPTER 13 A/D CONVERTER 2
User’s Manual U18279EJ3V0UD
(5) The INTAD2 interrupt request signal is generated
(6) Return to (2)
(7) To end the conversion, the AD2CE bit = 0 (stop)
A/D converter 2
Note
.
AD2CR0
AD2CR1
AD2CR2
AD2CR3
AD2CR4
AD2CR5
AD2CR6
AD2CR7
707