UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 626

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
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Cautions 1. In the A/D trigger mode or the A/D trigger polling mode, conversion is triggered when 1 is
2. If the ADnSCM register is written during A/D conversion operation (ADnCS bit = 1), the
3. Make sure that time of at least five basic clocks (f
4. The ADnCS bit remains set (1) when the conversion channel is changed during
5. It is recommended to set the A/D power save mode (ADnPS bit = 0) when the A/D
6. The setting procedure is as follows when an A/D conversion operation is started (after
7. The setting procedure is as follows when an A/D conversion operation is stopped.
8. It is recommended to set the A/D power save mode even in the IDLE and STOP modes.
9. Be sure to set bits 0, 2 to 6 and 11 to 13 to “0”.
written to the ADnCE bit.
In the hardware trigger mode, the conversion channel specification mode, or the
extension buffer mode, the trigger signal wait state starts when 1 is written to the ADnCE
bit.
The ADnCE bit is not cleared to 0 even after the A/Dn conversion end interrupt request
signal (INTADn) is generated in all modes.
therefore, write 0 to the ADnCE bit.
operation is performed as follows in each mode. The corresponding conversion result
register is undefined during A/D conversion operation.
• In A/D trigger mode, A/D trigger polling mode
• In hardware trigger mode, conversion channel specification mode, extension buffer
data to the ADnSCM register when the conversion operation is enabled (ADnCE bit = 1).
Otherwise, the register may not be set correctly.
The register can be successively written if the ADnCE bit is set to 1 after the ADnSCM
register is written when ADnCE bit = 0.
successive conversion.
converter is not used.
reset release and after recovery from the A/D power save mode (ADnPS bit = 0)).
Follow the setting procedure in Caution 6 above when releasing the IDLE or STOP mode
by using the reset signal.
<2> Set the A/D conversion time by using the ADnCTC.ADnFR3 to ADnFR0 bits.
<1> Select an input clock (f
<3> Set the ADnPS bit to 1 (A/D operation mode).
<4> Wait for 1
<5> Initialize A/D converters 0 and 1.
<6> Set the ADnCE bit to 1 (enable conversion operation).
<1> Set the ADnCE bit to 0 (stop conversion operation) (retaining ADnPS bit = 1).
<2> Set the ADnPS bit to 0 (A/D power save mode).
<3> Set the ADnOCKS.ADnOCKSEN bit to 0 (stop supplying the operating clock to A/D
A/D conversion is stopped and executed again from the beginning.
mode
A/D conversion is stopped and the trigger standby state is restored again.
bit to 1 (enable supplying the operating clock to A/D converter n).
converter n).
μ
s or longer after <3>.
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
AD01
) by using the ADnOCKS register and set the ADnOCKSEN
To stop the A/D conversion operation,
AD01
) passes before successively writing
(2/2)