UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 621

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Selector
(2) Sample & hold circuit
(3) Voltage comparator
(4) Array
(5) Successive approximation register (SAR)
The selector selects the analog input pin according to the mode set by the ADnSCM, ADnCTC, ADnCHEN,
ADnCTL0, ADnTSEL, ADnCH1, ADnCH2, ADLTS1, ADLTS2, and ADnOCKS registers and sends the input to
the sample & hold circuit (n = 0, 1).
ANI05, ANI15 to ANI17 are provided with an operational amplifier for input level amplification and an
overvoltage detection comparator. The operational amplifier and comparator of each analog input pin can be
specified to be on or off. The amplification (gain) of the operational amplifier can be selected from 2.5 to 10
times for ANI05, ANI15 to ANI17.
The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit,
and sends them to the voltage comparator. When the operational amplifier for input level amplification is used,
the gain specified by the OPnCTL0.OPnGA3 to OPnCTL0.OPnGA0 bits × the input voltage is sampled. This
circuit also holds the sampled analog input voltage during A/D conversion.
This comparator compares the voltage generated from the voltage tap of the array with the analog input
voltage. If the analog input voltage is found to be greater than the reference voltage (1/2 AV
of the comparison, the most significant bit (MSB) of the successive approximation register (SAR) is set. If the
analog input voltage is less than the reference voltage (1/2 AV
After that, bit 10 of the SAR is automatically set, and the next comparison is made. The voltage tap of the
array is selected by the value of bit 11, to which the result has been already set.
The voltage tap of the array and the analog input voltage are compared and bit 10 of the SAR is manipulated
according to the result of the comparison.
Comparison is continued like this to bit 0 of the SAR.
The array generates the comparison voltage input from an analog input pin.
The SAR is a 12-bit register that sets voltage tap data whose values from the array match the voltage values of
the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR (conversion results) are held in A/Dn conversion result registers 0 to 15 (ADnCR0 to ADnCR15) (n =
0, 1). In the extension buffer mode, however, the conversion result is stored in A/Dn conversion result
extension buffer registers 0 to 4 and, when selection load trigger x is generated, shifted to and stored in the
ADnECR0 to ADnECR4 registers (x = 1, 2). When all the specified A/D conversion operations have ended, an
A/Dn conversion end interrupt request signal (INTADn) is generated.
Bit 11 = 0: (1/4 AV
Bit 11 = 1: (3/4 AV
Analog input voltage ≥ Voltage tap of array: Bit 10 = 1
Analog input voltage ≤ Voltage tap of array: Bit 10 = 0
REFPn
REFPn
)
)
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
REFPn
), the MSB of the SAR is reset.
REFPn
) as a result
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