UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 816

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

814
(a) How to use CBnSCE bit
(i) In single reception mode
(ii) In continuous reception mode
<1> When the reception of the last data is ended with INTCBnR interrupt servicing, clear the CBnSCE
<2> When the reception is disabled after the reception of the last data has been ended, check that
<1> Clear the CBnSCE bit to 0 during reception of the last data with INTCBnR interrupt servicing by
<2> After receiving the INTCBnR signal of the last reception, read the last data from the CBnRX
<3> When the reception is disabled after the reception of the last data has been ended, check that
Caution In continuous reception mode, the serial clock is not stopped until the reception
bit to 0, and then read the CBnRX register.
the CBnSTR.CBnTSF bit is 0, and then clear the CBnPWR and CBnRXE bits to 0. To continue
reception, set the CBnSCE bit to 1 and start the next receive operation by performing a dummy
read of the CBnRX register.
the reception before the last reception, and then read the CBnRX register.
register.
the CBnSTR.CBnTSF bit is 0, and then clear the CBnPWR and CBnRXE bits to 0. To continue
reception, set the CBnSCE bit to 1 and start the next receive operation by performing a dummy
read of the CBnRX register.
executed when the CBnSCE bit is cleared to 0 is ended after the reception is started
by a dummy read.
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
User’s Manual U18279EJ3V0UD