UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 441

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(d) TMTn counter read buffer register (TTnCNT)
(e) TMTn capture/compare register 0 (TTnCCR0)
(f) TMTn capture/compare register 1 (TTnCCR1)
By reading the TTnCNT register, the count value of the 16-bit counter can be read.
If the TTnCCR0 register is set to D
Interval = (D
The TTnCCR1 register is not used in the interval timer mode. However, the set value of the TTnCCR1
register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches
the value of the CCR1 buffer register, the TOTm1 pin output is inverted and a compare match interrupt
request signal (INTTTEQCn1) is generated.
By setting this register to the same value as the value set in the TTnCCR0 register, a PWM waveform
with a duty factor of 50% can be output from the TOTm1 pin.
When the TTnCCR1 register is not used, it is recommended to set its value to FFFFH. Also mask the
register by the interrupt mask flag (TTnCCIC1.TTnCCMK1).
Remarks 1. TMTm control register 2 (TTmCTL2), TMTm I/O control register 1 (TTmIOC1), TMTm I/O
2. V850E/IF3: m = 1, n = 0, 1
Figure 8-9. Register Setting for Interval Timer Mode Operation (2/2)
0
+ 1) × Count clock cycle
control register 2 (TTmIOC2), TMTm I/O control register 3 (TTmIOC3), TMTn option
register 0 (TTnOPT0), TMTm option register 1 (TTmOPT1), TMTm capture input select
register (TTISLm), and TMTm counter write register (TTmTCW) are not used in the
interval timer mode.
V850E/IG3: m = 0, 1, n = 0, 1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
User’s Manual U18279EJ3V0UD
0
, the interval is as follows.
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