UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1061

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.2 Debugging Without Using DCU
(RXDA0, TXDA0) or CSIB0 pins (SIB0, SOB0, SCKB0, HS (P43)) as debug interfaces, without using the DCU.
26.2.1 Circuit connection examples
The following describes how to implement an on-chip debug function using MINICUBE2 with the UARTA0 pins
Remark See Table 26-4 for pins used when UARTA0 or CSIB0 is used for communication interface.
Notes 1. Connect TXDA0/SOB0 (transmit side) of the V850E/IF3 and V850E/IG3 to RXD/SI (receive side) of
Figure 26-4. Circuit Connection Example When UARTA0/CSIB0 Is Used for Communication Interface
2. The V850E/IF3, V850E/IG3-side pin connected to this pin (FLMD0, FLMD1) can be used as an
3. This connection is designed assuming that the RESET signal is output from the N-ch open-drain
4. EV
5. EV
6. The circuit enclosed by broken lines is designed for flash self programming, which controls the
the target connector, and TXD/SO (transmit side) of the target connector to RXDA0/SIB0 (receive
side) of the V850E/IF3 and V850E/IG3.
alternate-function pin other than while the memory is rewritten during a break in debugging, because
this pin is in a Hi-Z state.
buffer (output resistance: 100 Ω or less).
FLMD0 pin via ports. Use the port for inputting or outputting the high level. When flash self
programming is not performed, a pull-down resistance for the FLMD0 pin can be within 1 to 10 kΩ.
SS0
DD0
RESET_IN
, EV
, EV
RESET_OUT
QB-MINI2
TXD/SO
RXD/SI
FLMD1
FLMD0
SS1
DD1
, EV
, EV
GND
VDD
SCK
Note 1
Note 1
CLK
Note 2
Note 2
Note 3
HS
SS2
DD2
(V850E/IG3 only), V
(V850E/IG3 only), V
CHAPTER 26 ON-CHIP DEBUG FUNCTION
5 V
User’s Manual U18279EJ3V0UD
10 kΩ
1 to 10 kΩ
1 to 10 kΩ
SS0
DD0
, V
1 to 10 kΩ
, V
5 V
5 V
SS1
DD1
1 kΩ
5 V
, AV
, AV
3 to 10 kΩ
SS0
DD0
1 to 10 kΩ
, AV
, AV
10 kΩ
SS1
RESET signal
DD1
5 V
, AV
, AV
100 Ω
SS2
DD2
V850E/IF3, V850E/IG3
Note 5
Note 4
RESET
TXDA0/SOB0
RXDA0/SIB0
SCKB0
P43
FLMD1
FLMD0
Port X
Reset circuit
Note 6
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