UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 659

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UPD70F3451GC-UBT-A

Manufacturer Part Number
UPD70F3451GC-UBT-A
Description
MCU 32BIT 128KB FLASH 80LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet

Specifications of UPD70F3451GC-UBT-A

Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3451GC-UBT-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(10) Next, bit 10 of the successive approximation register (SAR) is automatically set, and the next comparison is
(11) When comparison of 12 bits has been completed, the valid digital value result remains in the successive
started. The voltage tap of the array is selected according to the value of bit 11, to which the result has been
already set.
The voltage tap of the array and the analog input voltage are compared and bit 10 of the SAR is manipulated
according to the result of the comparison.
Comparison is continued like this to bit 0 of the SAR.
approximation register (SAR). This value is transferred to A/Dn conversion result register m (ADnCRm) and
the conversion result is stored in this register in the A/D trigger mode, A/D trigger polling mode, hardware
trigger mode, and conversion channel specification mode (n = 0, 1, m = 0 to 15). The valid digital value is
stored in the A/Dn conversion result extension buffer register a in the extension buffer mode, and is shifted to
A/Dn conversion result extension register a when selection load trigger x is generated and stored (x = 1, 2, a =
0 to 4). When A/D conversion has ended the specified number of times, an A/Dn conversion end interrupt
request signal (INTADn) is generated.
Bit 11 = 0: (1/4AV
Bit 11 = 1: (3/4AV
Analog input voltage ≥ Voltage tap of array: Bit 10 = 1
Analog input voltage ≤ Voltage tap of array: Bit 10 = 0
REFPn
REFPn
)
)
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
657

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