UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 210

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

208
Table 6-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Interval timer
External event counter
External trigger pulse output
One-shot pulse output
PWM output
Free-running timer
Pulse width measurement
(a) Function as compare register
(b) Function as capture register
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Notes 1. With the V850E/IF3, this mode is only for TAA2 and TAA4. With the V850E/IG3, this mode is only for
Remark
The TAAnCCR0 register can be rewritten even when the TAAnCTL0.TAAnCE bit = 1.
The set value of the TAAnCCR0 register is transferred to the CCR0 buffer register. When the value of the
16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal
(INTTAnCC0) is generated. If TOAm0 pin output is enabled at this time, the output of the TOAm0 pin is
inverted.
When the TAAnCCR0 register is used as a cycle register in the interval timer mode or the TAAmCCR0
register is used as a cycle register in external event count mode, external trigger pulse output mode, one-
shot pulse output mode, or PWM output mode, the value of the 16-bit counter is cleared (0000H) if its
count value matches the value of the CCR0 buffer register.
The compare register is not cleared by setting the TAAnCTL0.TAAnCE bit to 0.
When the TAAmCCR0 register is used as a capture register in the free-running timer mode, the count
value of the 16-bit counter is stored in the TAAmCCR0 register if the valid edge of the capture trigger input
pin (TIAm0 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter
is stored in the TAAmCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the
capture trigger input pin (TIAm0 pin) is detected.
Even if the capture operation and reading the TAAmCCR0 register conflict, the correct value of the
TAAmCCR0 register can be read.
The capture register is cleared by setting the TAAmCTL0.TAAmCE bit to 0.
Remark
2. Writing to the TAAmCCR1 register is the trigger.
Operation Mode
Note 1
TAA2 to TAA4.
For anytime write and batch write, see 6.6 (2) Anytime write and batch write.
V850E/IF3: n = 0 to 4, m = 2, 4
V850E/IG3: n = 0 to 4, m = 2 to 4
Note 1
Note 1
Note 1
Note 1
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
Compare register
Compare register
Compare register
Compare register
Compare register
Capture/compare register
Capture register
User’s Manual U18279EJ3V0UD
Capture/Compare Register
Anytime write
Anytime write
Batch write
Anytime write
Batch write
Anytime write
None
How to Write Compare Register
Note 2
Note 2