UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 976

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

after single transfer has been completed. DMA channels 0 and 3 are used for single transfer. If two DMA transfer
request signals become active at the same time, two DMA transfer operations are alternately executed.
issued one clock after single transfer has been completed. DMA channels 0, 2, and 3 are used for single transfer. If
three or more DMA transfer request signals become active at the same time, two DMA transfer operations are
alternately executed, starting from the one with the highest priority.
974
(internal signal)
(internal signal)
(internal signal)
(internal signal)
(internal signal)
Figure 19-3 is an example of single transfer where a DMA transfer request with a lower priority is issued one clock
Figure 19-4 is an example of single transfer where two or more DMA transfer requests with a lower priority are
Note The bus is always released.
Note The bus is always released.
DMARQ0
DMARQ3
DMARQ0
DMARQ2
DMARQ3
CPU DMA3 CPU DMA3 CPU DMA2
CPU CPU
Note
DMA0
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
Note
CPU
Note
Figure 19-3. Single Transfer Example 3
Figure 19-4. Single Transfer Example 4
DMA0
Note
Note
CPU DMA0
CPU DMA3
User’s Manual U18279EJ3V0UD
Note
CPU DMA2
Note
CPU DMA0
Note
DMA channel 0
terminal count
CPU DMA0
DMA channel 3
terminal count
Note
CPU DMA3
Note
CPU DMA2
Note
CPU DMA0 CPU DMA0 CPU
Note
CPU DMA3
Note
DMA channel 2
terminal count
Note
CPU DMA2
Note
DMA channel 0
terminal count
Note
DMA channel 3
terminal count
CPU
DMA0
DMA3
CPU CPU
CPU CPU