UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 727

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) UARTAn option control register 0 (UAnOPT0)
(5) UARTAn status register (UAnSTR)
Caution Be sure to set bits 3 and 5 to 7 to “0”, and set bits 2 and 4 to “1”. Operation with other
The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of UARTAn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents.
This register can be read or written in 8-bit or 1-bit units, but the UAnTSF bit is a read-only bit, while the
UAnPE, UAnFE, and UAnOVE bits can both be read and written. However, these bits can only be cleared by
writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained).
The initialization conditions are shown below.
Caution Be sure to read and check the error flags of the UAnPE, UAnFE, and UAnOVE bits, and clear
settings is not guaranteed.
(n = 0 to 2)
UAnOPT0
UAnSTR register
UAnTSF bit
UAnPE, UAnFE, UAnOVE bits
the flags by writing “0” to them.
After reset: 14H
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
UAnRDL
UAnTDL
• The output level of the TXDAn pin can be inverted using the UAnTDL bit.
• This register can be set when the UAnCTL0.UAnPWR bit = 0 or when the
• The input level of the RXDAn pin can be inverted using the UAnRDL bit.
• This register can be set when the UAnPWR bit = 0 or the UAnCTL0.UAnRXE bit = 0.
• When the UAnRDL bit is set to 1 (inverted input of receive data), reception must be
enabled (UAnCTL0.UAnRXE bit = 1) after setting the data reception pin to the
UART reception pin (RXDAn) when reception is started. When the pin mode is
changed after reception is enabled, the start bit will be mistakenly detected if the
pin level is high.
UAnCTL0.UAnTXE bit = 0.
0
1
0
1
0
Register/Bit
7
Normal output of transfer data
Inverted output of transfer data
Normal input of transfer data
Inverted input of transfer data
R/W
6
0
Address: UA0OPT0 FFFFFA03H, UA1OPT0 FFFFFA13H,
User’s Manual U18279EJ3V0UD
5
0
UA2OPT0 FFFFFA23H
4
1
• After reset
• UAnCTL0.UAnPWR bit = 0
• UAnCTL0.UAnTXE bit = 0
• 0 write
• UAnCTL0.UAnRXE bit = 0
Transmit data level bit
Receive data level bit
3
0
Initialization Conditions
2
1
UAnTDL UAnRDL
1
0
725