UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 963

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3 Control Registers
19.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3)
registers are divided into two 16-bit registers, DSAnH and DSAnL.
register, a new transfer source address for DMA transfer can be specified during DMA transfer (see 19.8 Next
Address Setting Function). When setting the next address, the newly set value of the DSAn register is transferred
to the slave register and becomes valid only when DMA transfer has been completed normally and the DCHCn.TCn
bit is set to 1, or when the DCHCn.INITn bit is set to 1 (n = 0 to 3). However, the set value of the DSAn register is
invalid even when the DCHCn.Enn bit is cleared to 0 to disable DMA transfer and then the DSAn register is set.
The DSA0 to DSA3 registers set the DMA transfer source address (28 bits) for DMA channel n (n = 0 to 3). These
Since these registers are configured as 2-stage FIFO buffer registers consisting of the master register and slave
(1) DMA source address registers 0H to 3H (DSA0H to DSA3H)
The DSA0H to DSA3H registers can be read or written in 16-bit units.
Reset makes these registers undefined.
Cautions 1. When setting an address of an on-chip peripheral I/O register for the source address, be
Caution Be sure to set bits 14 to 12 to “0”. If they are set to “1”, the operation is not guaranteed.
(n = 0 to 3)
DSAnH
2. Do not set the DSAnH register while DMA is suspended.
After reset:
sure to specify an address between FFFF000H and FFFFFFFH. An address of the on-chip
peripheral I/O register image (3FFF000H to 3FFFFFFH) must not be specified.
SAn27 to
SAn16
SAn23
Undefined
IRSn
IRSn
15
0
1
7
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
On-chip peripheral I/O
Internal RAM
Set the DMA transfer source address (A27 to A16). During DMA transfer,
these bits store the next DMA transfer source address.
SAn22
14
0
6
R/W
User’s Manual U18279EJ3V0UD
SAn21
Address: DSA0H FFFFF082H, DSA1H FFFFF08AH,
13
0
5
DMA transfer source specification
SAn20
12
DSA2H FFFFF092H, DSA3H FFFFF09AH
0
4
SAn27
SAn19
11
3
SAn26
SAn18
10
2
SAn25
SAn17
9
1
SAn24
SAn16
8
0
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