UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 302

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

300
(4) TABn I/O control register 1 (TABnIOC1)
The TABnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals
(TIBn0 to TIBn3 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Cautions 1. Rewrite the TABnIS7 to TABnIS0 bits when the TABnCTL0.TABnCE bit = 0. (The same
TABnIOC1
(n = 0, 1)
2. The TABnIS7 to TABnIS0 bits are valid only in the free-running timer mode (only when
After reset: 00H
value can be written when the TABnCE bit = 1.) If rewriting was mistakenly performed,
clear the TABnCE bit to 0 and then set the bits again.
the TABnOPT0.TABnCCSa bit = 1) and the pulse width measurement mode (a = 0 to 3).
In all other modes, a capture operation is not possible.
TABnIS7
TABnIS5
TABnIS3
TABnIS1
TABnIS7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
7
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
R/W
TABnIS6 TABnIS5 TABnIS4 TABnIS3 TABnIS2 TABnIS1 TABnIS0
TABnIS6
TABnIS4
TABnIS2
TABnIS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
6
Address: TAB0IOC1 FFFFF5E3H, TAB1IOC1 FFFFF623H
User’s Manual U18279EJ3V0UD
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Capture trigger input signal (TIBn2 pin) valid edge detection
Capture trigger input signal (TIBn3 pin) valid edge setting
Capture trigger input signal (TIBn1 pin) valid edge setting
Capture trigger input signal (TIBn0 pin) valid edge setting
5
4
3
2
1
0