UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 473

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOTm1 pin.
After the one-shot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger.
When the trigger is generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again
while the one-shot pulse is being output, it is ignored.
count value matches the value of the CCR0 buffer register.
(INTTTEQCm1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer
register.
is used as the trigger.
When the TTmCE bit is set to 1, 16-bit timer/event counter T waits for a trigger. When the trigger is generated, the
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal (INTTTEQCm0) is generated when the 16-bit counter counts after its
The valid edge of an external trigger input (EVTTm pin) or setting the software trigger (TTmCTL1.TTmEST bit) to 1
Remark
INTTTEQCm0 signal
INTTTEQCm1 signal
External trigger input
TTmCCR0 register
TTmCCR1 register
(EVTTm pin input)
TOTm0 pin output
TOTm1 pin output
Output delay period = (Set value of TTmCCR1 register) × Count clock cycle
Active level width = (Set value of TTmCCR0 register − Set value of TTmCCR1 register + 1) × Count clock cycle
16-bit counter
TTmCE bit
V850E/IF3: m = 1
V850E/IG3: m = 0, 1
FFFFH
0000H
Figure 8-26. Basic Timing in One-Shot Pulse Output Mode
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
Delay
(D
D
1
1
)
Active
level width
(D
D
User’s Manual U18279EJ3V0UD
0
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
D
D
The compare match interrupt request signal
0
0
1
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)
471