UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 522

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

520
Figure 8-55. Operation Example (When TTmSCE Bit = 0, TTmECS1 and TTmECS0 Bits = 01, and TTmUDS1 and
Table 8-11. Relationship Between TTmSCE Bit and TTmZCL, TTmBCL, TTmACL, TTmECS1, and TTmECS0 Bits
Clearing Method
(TENCm0 pin input)
(TENCm1 pin input)
(6) Clearing counter to 0000H by encoder clear signal (TECRm pin)
Encoder clear input
Remark
(TECRm pin input)
TTmCNT register
Peripheral clock
The 16-bit counter can be cleared to 0000H by the input signal of the TECRm pin in two ways which are
selected by the TTmIOC3.TTmSCE bit.
TTmIOC3.TTmZCL, TTmIOC3.TTmBCL, TTmIOC3.TTmACL, TTmIOC3.TTmESC1, and TTmIOC3.TTmECS0
bits.
The counter can be cleared by the methods described below only in the encoder compare mode.
(a) Clearing method <1>: By detecting edge of encoder clear signal (TECRm pin) (TTmSCE bit = 0)
<1>
<2>
Encoder input
Encoder input
timing signal
INTTIECm
When the TTmSCE bit = 0, the 16-bit counter is cleared to 0000H in synchronization with the peripheral
clock if the valid edge of the TECRm pin specified by the TTmECS1 and TTmECS0 bits is detected. At this
time, an encoder clear interrupt request signal (INTTIECm) is generated. When the TTmSCE bit = 0,
setting of the TTmZCL, TTmBCL, and TTmACL bits is invalid.
V850E/IF3: m = 1
V850E/IG3: m = 0, 1
Count
TTmSCE Bit
0
1
N
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
TTmZCL Bit
Invalid
Valid
N + 1
User’s Manual U18279EJ3V0UD
Counter clear
TTmUDS0 Bits = 11)
The TTmSCE bit also controls, depending its setting, the
TTmBCL Bit
0000H
Invalid
Valid
0001H
TTmACL Bit
Invalid
Valid
TTmECS1, TTmECS0 Bits
0002H
Invalid
Valid