UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 782

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.7.4 Receive operation
to 1. RXDB pin sampling begins and a start bit is detected. When the start bit is detected, the receive operation
begins, and data is stored sequentially in the receive shift register according to the baud rate that was set.
each time the reception of one frame of data is completed. Normally, the receive data is transferred from the UBRX
register to memory by this interrupt servicing.
number set as the trigger by the UBFIC2.UBRT3 to UBFIC2.UBRT0 bits are transferred to receive FIFO.
set as the trigger by the UBFIC2.UBRT3 to UBFIC2.UBRT0 bits can be read from receive FIFO.
stored in receive FIFO (0 bytes or more) can be read from receive FIFO by referencing the number of receive data
specified as the trigger by the UBRT3 to UBRT0 bits (1 byte) or the UBFIS0 register.
780
The awaiting reception state is set by setting the UBCTL0.UBPWR bit to 1 and then setting the UBCTL0.UBRXE bit
In the single mode (UBFIC0.UBMOD bit = 0), a reception end interrupt request signal (INTUBTIR) is generated
In the FIFO mode (UBFIC0.UBMOD bit = 1), the INTUBTIR signal occurs when as many receive data as the
If the pending mode is specified (UBFIC0.UBIRM bit = 0) in the FIFO mode, as many receive data as the number
If the pointer mode is specified (UBFIC0.UBIRM bit = 1) in the FIFO mode, as many data as the number of bytes
Caution If the pointer mode is specified in the FIFO mode and if as many data as the number of bytes
(1) Reception enabled state
(2) Starting a receive operation
This state is set by the UBCTL0.UBRXE bit.
• UBRXE = 1: Reception enabled state
• UBRXE = 0: Reception disabled state
However, because this bit is also used by CSIB2, enable reception after setting the CB2CTL0.CB2PWR bit to
0 and disabling the CSIB2 operation.
In the reception disabled state, the reception hardware stands by in the initial state. At this time, the
reception end interrupt request signal or reception error interrupt request signal does not occur, and the
contents of the receive data register (UBRX register in the single mode or receive FIFO in the FIFO mode
(UBRXAP register)) are retained.
A receive operation is started by the detection of a start bit.
The RXDB pin is sampled using the serial clock from UARTB control register 2 (UBCTL2).
stored in receive FIFO are read by referencing the UBFIS0 register, no data may be stored in
receive FIFO (UBFIS0.UBRB4 to UBFIS0.UBRB0 bits = 00000) even though the reception end
interrupt request signal (INTUBTIR) has occurred. In this case, do not read data from receive
FIFO. Be sure to read data from receive FIFO after confirming that the number of bytes stored
in receive FIFO = 1 byte or more (UBRB4 to UBRB0 bits = other than 00000).
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD