UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 316

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(1) Counter basic operation
This section explains the basic operation of the 16-bit counter. For details, refer to the description of the
operation in each mode.
Remark
(a) Counter start operation
(b) Clear operation
(c) Overflow operation
(d) Counter read operation during count operation
(e) Interrupt operation
• In external event count mode
• In modes other than the above
The 16-bit counter is cleared to 0000H when its value matches the value of the compare register and when
its value is captured. The count operation from FFFFH to 0000H that takes place immediately after the
counter has started counting or when the counter overflows is not a clearing operation. Therefore, the
INTTBnCCa interrupt signal is not generated.
The 16-bit counter overflows when the counter counts up from FFFFH to 0000H in the free-running mode
or pulse width measurement mode. If the counter overflows, the TABnOPT0.TABnOVF bit is set to 1 and
an interrupt request signal (INTTBnOV) is generated. Note that the INTTBnOV signal is not generated
under the following conditions.
• Immediately after a count operation has been started
• If the counter value matches the compare value FFFFH and is cleared
• When FFFFH is captured in the pulse width measurement mode and the counter counts up from FFFFH
The value of the 16-bit counter of TABn can be read by using the TABnCNT register during the count
operation.
When the TABnCTL0.TABnCE bit = 1, the value of the 16-bit counter can be read by reading the TABnCNT
register. When the TABnCE bit = 0, the 16-bit counter is FFFFH and the TABnCNT register is 0000H.
TABn generates the following five interrupt request signals.
• INTTBnCC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer
• INTTBnCC1 interrupt: This signal functions as a match interrupt request signal of the CCR1 buffer
to 0000H
Caution After the overflow interrupt request signal (INTTBnOV) has been generated, be sure to
When the TABnCTL0.TABnCE bit is set from 0 to 1, the 16-bit counter is set to 0000H.
After that, it counts up to 0001H, 0002H, 0003H, … each time the valid edge of external event count
input (EVTBn) is detected.
Starts counting from the default value FFFFH in all modes.
It counts up from FFFFH to 0000H, 0001H, 0002H, 0003H, and so on.
n = 0, 1
a = 0 to 3
check that the overflow flag (TABnOVF bit) is set to 1.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
register and as a capture interrupt request signal to the TABnCCR0 register.
register and as a capture interrupt request signal to the TABnCCR1 register.
User’s Manual U18279EJ3V0UD